1. Field of the Invention
Embodiments of the present invention relate to a memory device such as a charge trapping type non-volatile memory device and a method of manufacturing the same. More particularly, embodiments of the present invention relate to a memory device such as a charge trapping type non-volatile memory device including a cell transistor having a desired sidewall profile and configured to reduce charge spreading, and a method of manufacturing the same.
2. Description of the Related Art
Generally, non-volatile semiconductor memory devices include floating gate type non-volatile memory devices and charge trapping type non-volatile memory devices, the types corresponding to the structures of the respective unit memory cells. In the floating gate type memory device, a unit memory cell typically includes a tunnel oxide layer formed on a semiconductor substrate, as well as a floating gate, a dielectric layer and a control gate. Data may be stored in the floating gate as free charges that are injected into the floating gate.
Charges injected into the floating gate may dissipate if defects occur in the tunnel oxide layer, which is disposed between the substrate and the floating gate. In order to reduce or prevent such dissipation, the thickness of the tunnel oxide layer of the floating gate type memory device may be increased. However, a high driving voltage may be required when the floating gate type memory device has a thick tunnel oxide layer. Accordingly, a structure of a peripheral circuit for the floating gate type memory device may become more complicated. As a result, it may be difficult to achieve high levels of integration for the floating gate type memory device.
The charge trapping type memory device may have a silicon-oxide-nitride-oxide-semiconductor (SONOS) structure, which may be referred to as a SONOS type non-volatile memory device. In the SONOS type non-volatile memory device, the unit memory cell may include a tunnel oxide layer on the semiconductor substrate, a charge trapping layer, a dielectric layer, and an electrode. Data may be stored into the SONOS type non-volatile memory device corresponding to charges injected into charge trapping sites of the charge trapping layer. For example, charges may be trapped in deep-level trapping sites of a silicon nitride layer, while the tunnel oxide layer may be relatively thin.
In the conventional SONOS type non-volatile memory device, charges may be considered to be fixed in the charge trapping sites. Accordingly, memory cells of the conventional SONOS type non-volatile memory device may have charge trapping layer patterns, e.g., the silicon nitride layer patterns, connected to one another. For example, adjacent silicon nitride layer patterns may be connected to one another, rather than being discrete patterns such as island-shaped silicon nitride layer patterns.
However, in such a configuration, charges stored in the charge trapping layer patterns may move, e.g., in a horizontal direction along a plane of the charge trapping layer patterns, after the charges are stored therein. If the stored charges migrate horizontally, a cell transistor may partially lose the stored charges, so that a threshold voltage of the cell transistor may not reach a desired level. Thus, data stored in the memory cell of the conventional SONOS type non-volatile memory device may be deteriorated or undesirably changed.
In order to reduce or eliminate charge migration, the charge trapping type memory device may have a discrete charge trapping layer pattern, e.g., an island shape that is not connected to an adjacent memory device. For example, a silicon nitride layer may be patterned in two directions, e.g., along an X-axis direction and a Y-axis direction, in order to isolate the silicon nitride layer of one memory cell from an adjacent memory cell.
To form a charge trapping type memory device having a discrete charge trapping layer pattern, the tunnel oxide layer, the charge trapping layer and a dielectric layer may be formed on a substrate, and these layers may be etched to form a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern. Thus, each of the tunnel oxide layer pattern, the charge trapping layer pattern and the dielectric layer pattern may have a same discrete shape on the substrate, i.e., they may be stacked on the substrate.
However, it may be difficult to implement such an approach for some high dielectric constant materials, e.g., if the dielectric layer is formed of a metal oxide. In particular, it may be difficult to pattern the dielectric layer using a plasma-based dry etching process. For example, the dielectric layer may be thin and the etching process for forming the dielectric layer pattern may be somewhat excessively carried out.
When performing etching processes for patterning a silicon nitride layer and a tunnel oxide layer after etching the dielectric layer, a sidewall of an electrode formed on the dielectric layer pattern may be seriously damaged, and a cell transistor of the charge trapping type non-volatile memory device may have a poor sidewall profile. As a result, the resistance of the electrode may increase, electrical characteristics of the charge trapping type non-volatile memory device may deteriorate due to a reduced width of the electrode, etc.